CRN# 21952 ECET 14600-02M
CRN# 23450 ECET 14600-03M

Digital Circuits II
Hybrid Classes (Online Lecture)
CRN# 21952 Section, 7:30-9:20 PM, Tuesday, Lab in Room ET 215
CRN# 23450 Section, 1:00-2:50
PM, WEdnesday, Lab in Room ET 305

Spring 2015

Paul I. Lin, Professor of Electrical & Computer Engr. Tech. pilin@purdue.edu
TA: Josh Stetzel, stetjj01@students.ipfw.edu

 

Class Materials/Activities
Date
January 13, 2015;
Grading Policy, 4/8/2015 announcement: 2 Tests (30%), Hw & Labs (35%), Final Project (25%), Class Participation (10%)
Weeks 1, 2, 3, 4, 5, 6, 7, 8, 10, 12,13, 14, 15 (April 28/29)- Lecture note (Available);
Echo 360 Recoreded Lectures (available)

Announcement Exam 2 (50 min) - April 14/15 (Coverage areas of Exam 2)
Exam 1 - Feb. 24/25
(review of Exam 1);
Lab and Homework Assignments

Final Project - Traffic Light Controller (4/7 to 5/5; 4/8 to 5/6)
Final Project (project period 4/7 to 5/5; 4/8 to 5/6) - Traffic Light Controller Simulation
** Team-based project (2 student per team)
** Deliverables/Items due May 5 and May 6:
**** One final project report, one PPT file presentation, and Demo
**** Project file (in zipped) format
(see Final Project page for details)
Progress Report 2 due 4/24 (Report guideline posted)
Progress Report 1 due 4/17 (Report guideline posted)
Hw 3 Assigned April 1, due April 13 (VHDL Examples of Chapters 11 and 12; plus Visio drawing for Flowchart
Hw 3 Assigned April 1, due April 13 (VHDL Examples of Chapters 11 and 12; plus Visio drawing for Flowchart
Lab 6 Assigned March 26, due April 8 (Lab 6 discussion - April 1, Echo 360 recorded)
Hw 2 Assigned March 17/18, due March 27
Lab 5 Assigned March 3/4, due March 17/18
Lab 4 Assigned Feb. 17/18, due March 3/4
Lab 3 Assigned Feb. 10/11, due Feb 24/25 (Lab demo posted)
Lab 2 Assigned Jan. 27/28, due Feb 10/11
Lab 1 Assigned Jan. 20/21, due Feb. 3/4
Hw 1 Assigned Feb. 9, due Feb. 16 (Chapter 4 problems)




Reading Assignments:

Read Ch. 7 of text book; Lecture 8

Lab Demos & Illustration Activities 

* Demo-Tutorial Altera Qurtus II, 32 min video, Paul I. Lin, 2015/1/21
*Quartus II Online Demonstration, Altera Demo Center: Quartus II Software Overview (Video 4:51 min);  Basic FPGA/CPLD Design; Design Flows: Design Optimization and Implementation; Reducing Design Cycles; Verification
* The Next Industrial Revolution: Low-Cost Cyclone III FPGA, Altera Webinar, 25 min
Altera: Qurtus II and Product References * VHDL, Altera, http://www.altera.com/support/examples/vhdl/vhdl.html
* Recommenede HDL Coding Style chapter 6 of the Qurtus II Handbook
* Download Altera Quartus II 9.1 from Prof. Hack's Web site
Xilinx Products & References * Xilinx Virtex UtraScale VU440 FPGA Demo (7:22 min)
* UltraScale Integrated 100G Ethernet IP
References * Altera DE0 Development and Education Board, Cyclone III EP3C16484 FPGA,, Getting Started Guide, DE0 User Manual, Quartus II Setting file with pin assignments for DE0 board (download from Prof. Lin's link: DE0.QSF file)
Quartus II Setting File with Pin Assignments for DE0
** Lattice FPGA/CPLD

 

Email Professor Paul I. Lin lin@ipfw.edu

Back to Prof. Lin's Homepage